Processor Architecture

• 26 hrs lectures
• 10 hrs pc labs
• 16 hrs projects

• 60 pts final exam (written part)
• 10 pts mid-term test (9 pts written part, 1 pts test part)
• 30 pts projects

Overview of processor microarchitecture and its future trends, ability to compare processors and using suitable tools, simulate the influence of changes in their architecture. Get acquainted with processor performance measurement. The knowledge of architecture and hardware support of parallel computation on graphic processors can be directly applied for acceleration of intensive calculations. 

To familiarize students with architecture of the newest processors exploiting the instruction-level, thread-level and data-level parallelism. To clarify the role of a compiler and its cooperation with CPU. To be able to orientate oneself on the processor market, to evaluate and compare various CPUs. Next to familiarize with architecture of graphical processors and its use for acceleration of numerical calculations (GPGPU), and with low-power techniques in processors for mobile applications.  

Von Neumann computer architecture, memory hierarchy, programming in assembly language, compiler's tasks and functions

• current PPT slides for lectures
• http://inst.eecs.berkeley.edu/~cs152/sp13/
• https://www.anandtech.com
• Agner Fog: Software optimization resources
• Intel Architecture Optimization Manual
• Nvidia CUDA SDK Manual
• Baer, J.L.: Microprocessor Architecture. Cambridge University Press, 2010, 367 s., ISBN 978-0-521-76992-1
• Hennessy, J.L., Patterson, D.A.: Computer Architecture - A Quantitative Approach. 5. vydání, Morgan Kaufman Publishers, Inc., 2012, 493 s., ISBN: 978-0-12-383872-8
• Kirk, D., and Hwu, W.: Programming Massively Parallel Processors: A Hands-on Approach, Elsevier, 2010, s. 256, ISBN: 978-0-12-381472-2
• Jeffers, J., and Reinders, J.: Intel Xeon Phi Coprocessor High Performance Programming, 2013, Morgan Kaufmann, p. 432), ISBN: 978-0-124-10414-3

1. Scalar processors. Pipelined instruction processing and compiler asistance
2. Superscalar CPU. Dynamic instruction scheduling, branch prediction.
3. Advanced superscalar processing techniques: register renaming, data flow through memory hierarchy.
4. Optimization of instruction and data fetching. Examples of superscalar CPUs.
5. Multi-threaded processors.
6. Data parallelism. SIMD extensions and vectorization.
7. Architecture of graphics processing units, SIMT programming model.
8. CUDA programming language, thread and memory model.
9. Synchronisation and reduction on GPU, design and tuning of GPU codes.
10. Stream processing, multi-GPU systems, GPU libraries.
11. Architecture of many core systems (MIC, Xeon Phi) and their programming.
12. VLIW processors. SW pipelining, predication, binary translation.
13. Low power processors.

1. Performance measurement for sequential codes.
2. Vectorisation using OpenMP 4.0.
3. CUDA: Memory transfers, simple kernels.
4. CUDA: Shared memory.
5. CUDA: Texture and constant memory, reduction operation.

• Performance evaluation and code optimization using OpenMP 4.0
• Acceleration of computational job using CUDA 8.0 

Assessment of two projects, 13 hours in total and, computer laboratories and a midterm examination.
Exam prerequisites:
To get 20 out of 40 points for projects and midterm examination.

• Missed labs can be substituted in alternative dates (monday or friday)
• There will be a place for missed labs in the last week of the semester.

To get 20 out of 40 points for projects and midterm examination.