Course details

The Principles of Testable Design Synthesis

PTD Acad. year 2020/2021 Winter semester

Current academic year

The course provides the state-of-the-art coverage in the field of digital systems testing and testable design. It deals with such diagnostic problems which must be solved by a digital circuit designer.

Guarantor

Language of instruction

Czech, English

Completion

Examination (written)

Time span

  • 39 hrs lectures

Department

Lecturer

Instructor

Study literature

  • M. Abramovici, M. A. Breuer, D. Friedman: Digital Systems Testing and Testable Design: Revised Printing, Computer Society Press, 1995, ISBN 0-7803-1062-4, 680 pp.
  • A. L. Crouch: Design-for-Test for Digital IC's and Embedded Core Systems, Prentice Hall, 1999, ISBN 0-13-084827-1, 347 pp.
  • P. Michel, U. Lauther, P. Duzzy: The Synthesis Approach to Digital System Design, The Kluwer International Series in Engineering and Computer Science, 1992, ISBN 0-7923-9199-3, 375 pp.

Syllabus of lectures

  • The Principles of Digital System Synthesis, the Implementation of Testability Principles during the Synthesis.
  • The Testability of a Digital Circuit, Controlability and Observability Concepts, Testability Measures.
  • The Evolution of Digital Circuit Testing Methods – the Principles of Increasing Controlability/Observability Parameters of Internal Nodes.
  • Test Points Techniques. The Implementation of Scan Registers to Increase Controlability/Observability
  • Full Scan Methods: Serial Methods (LSSD, Scan Path, Scan Set), Parallel Methods (RAS, ARAS).
  • Partial Scan Methods. The Utilisation of Full and Partial Scan Methods in Synthesis.
  • PLA Testing, Testable PLA Synthesis.
  • Built-in Self Test.
  • Test Pattern Generator, Test Response Analyser.
  • BIST Architectures, Hierarchical Structure of BIST Architectures.
  • CSTP, BILBO.
  • Self-checking design.
  • Boundary Scan. Test of Connections.

Course inclusion in study plans

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