Advanced Digital Systems

• 26 hrs lectures
• 10 hrs pc labs
• 16 hrs projects

• 60 pts final exam (written part)
• 18 pts mid-term test (written part)
• 10 pts labs
• 12 pts projects

To give the students the knowledge of advanced digital systems design including hardware description languages, professional CAD tools, techniques for constrained design, and PLD technology.
The students are able to design complex constrained digital systems using contemporary design techniques and they know modern methods for synthesis and verification of these systems.

Digital system design, basic programming skills.

• Přednáškové materiály v elektronické podobě.
• Khatri S. P., Gulati K. (eds.): Advanced Techniques in Logic Synthesis, Optimizations and Applications, ISBN 978-1-4419-7517-1, 2011
• Rabaey J., Pedram M.: Low Power Design Methodologies, Kluwer, ISBN 0792396308, 1996

• M. Morris Mano, Michael D. Ciletti: Digital Design, ISBN  978-9353062019, 2018
• Micheli G., High-Level Synthesis from Algorithm to Digital Circuit, ISBN 978-1-4020-8587-1, 2008

• Combinatorial and sequential logic design techniques, algorithms, and tools review.
• Review of digital design target technologies (ASIC, FPGA).
• Advanced synthesis techniques (pipelining, retiming).
• Constraint conditions.
• Models and methods for modern synthesis of digital circuits (AIG, BDD, SAT solvers).
• The modern synthesis of digital circuits (logic optimization).
• Modern synthesis of digital circuits (optimization for target technology).
• The synergy between synthesis and verification of digital circuits.
• Low power design methodologies.
• Development tools for FPGA and SoC.
• Verification of digital circuits (OVM methodology).

• Synthesis of the basic logic circuits, pipelining, retiming.
• Constraint conditions.
• Synthesis of basic digital circuits using ABC tool.
• Synthesis of advanced digital circuits using ABC tool.
• Verification of digital circuits.

• Individual project focused on synthesis of digital circuits.

Written mid-term exam and project in due dates.

Presence in any form of instruction is not compulsory. An absence (and hence loss of points) can be compensated in the following ways: 

1. presence in another laboratory group dealing with the same task. 
2. showing a summary of results to the tutor at the next lab. 
3. sending a short report (summarizing the results of the missed lab and answering the questions from the assignment) to the tutor, in 14 days after the missed lab.

Consultation after the lecture or exercise, or at any other time after an email agreement.