Course details

Hardware/Software Codesign

HSC Acad. year 2007/2008 Winter semester 5 credits

Current academic year

System-level aspects of computing systems design. Constrained and optimized HW/SW system design. Behavioral description. Models and implementation of basic HW and SW components and their interface. HW and SW components synthesis. Mapping of behavioral description onto components. Components interface synthesis. Scheduling of access to shared components. Techniques for prediction and analysis of constrained and optimized design. Partitioning algorithms and tools. Hardware synthesis and code generation. Verification. HW/SW computing architectures. Integrated HW/SW development systems. Optimized HW/SW systems case studies.

Guarantor

Fučík Otto, doc. Dr. Ing. (DCSY)

Language of instruction

Czech, English

Completion

Examination

Time span

  • 39 hrs lectures
  • 13 hrs projects

Department

Department of Computer Systems (UPSY)

Subject specific learning outcomes and competences

The students understand the theory and techniques of an automated hardware/software co-design of constrained computating systems.

Theoretical background for analyzis and design of HW/SW systems.

Learning objectives

To give the students the knowledge of hardware/software computing systems co-design techniques including behavioral modeling of both hardware and software components as well as their interaction, partitioning algorithms, analyzing and profiling techniques, simulation, synthesis, and verification of designed systems.

Prerequisite knowledge and skills

Basics of system simulation and design.

Syllabus of lectures

  • System-level aspects of computing systems design.
  • Constrained and optimized HW/SW system design.
  • Behavioral description.
  • Models and implementation of basic HW and SW components and their interface.
  • HW and SW components synthesis.
  • Mapping of behavioral description onto components.
  • Components interface synthesis.
  • Scheduling of access to shared components.
  • Techniques for prediction and analysis of constrained and optimized design.
  • Partitioning algorithms and tools.
  • Hardware synthesis and code generation. Verification.
  • HW/SW computing architectures. Integrated HW/SW development systems.
  • Optimized HW/SW systems case studies.

Progress assessment

Study evaluation is based on marks obtained for specified items. Minimimum number of marks to pass is 50.

Requirements for class accreditation are not defined.

Controlled instruction

Written mid-term exam and submitted project in due date.

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