Faculty of Information Technology, BUT

Ing.

Vojtěch Mrázek

Ph.D.

Research worker

+420 54114-1348
mrazek@fit.vut.cz
Office L307

Publications

  • 2019

    MRÁZEK Vojtěch, VAŠÍČEK Zdeněk, SEKANINA Lukáš, HANIF Muhammad A. and SHAFIQUE Muhammad. ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Denver, 2019, pp. 1-8.
    Detail

    MRÁZEK Vojtěch, HANIF Muhammad A., VAŠÍČEK Zdeněk, SEKANINA Lukáš and SHAFIQUE Muhammad. autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. In: The 56th Annual Design Automation Conference 2019 (DAC '19). Las Vegas: Association for Computing Machinery, 2019, pp. 1-6. ISBN 978-1-4503-6725-7.
    Detail

    VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Automated Circuit Approximation Method Driven by Data Distribution. In: Design, Automation and Test in Europe Conference. Florence: European Design and Automation Association, 2019, pp. 96-101. ISBN 978-3-9819263-2-3.
    Detail

    SEKANINA Lukáš, VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Automated Search-Based Functional Approximation for Digital Circuits. Approximate Circuits - Methodologies and CAD. Heidelberg: Springer International Publishing, 2019, pp. 175-203. ISBN 978-3-319-99322-5.
    Detail

    MRÁZEK Vojtěch, SEKANINA Lukáš, DOBAI Roland, SÝS Marek and ŠVENDA Petr. Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 99, no. 99, pp. 1-11. ISSN 1063-8210.
    Detail

    ANSARI Mohammad S., MRÁZEK Vojtěch, COCKBURN Bruce F., SEKANINA Lukáš, VAŠÍČEK Zdeněk and HAN Jie. Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 99, no. 99, p. 12. ISSN 1063-8210.
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  • 2018

    ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. ADAC: Automated Design of Approximate Circuits. In: Proceedings of 30th International Conference on Computer Aided Verification (CAV'18). Oxford, UK: Springer International Publishing, 2018, pp. 612-620. ISBN 978-3-319-96145-3.
    Detail

    MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and SEKANINA Lukáš. Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. In: Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems. Edinburgh: Institute of Electrical and Electronics Engineers, 2018, pp. 264-271. ISBN 978-1-5386-7753-7.
    Detail

    SEKANINA Lukáš, MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. In: 25th IEEE International Conference on Electronics Circuits and Systems (ICECS). Bordeaux: IEEE Circuits and Systems Society, 2018, pp. 377-380. ISBN 978-1-5386-9562-3.
    Detail

    MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Evolutionary Design of Large Approximate Adders Optimized for Various Error Criteria. In: Proceedings of the Genetic and Evolutionary Computation Conference Companion (GECCO '18). Kyoto: Association for Computing Machinery, 2018, pp. 294-295. ISBN 978-1-4503-5764-7.
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    MRÁZEK Vojtěch, SÝS Marek, VAŠÍČEK Zdeněk, SEKANINA Lukáš and MATYÁŠ Václav. Evolving Boolean Functions for Fast and Efficient Randomness Testing. In: Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '18). Kyoto: Association for Computing Machinery, 2018, pp. 1302-1309. ISBN 978-1-4503-5618-3.
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    MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and HRBÁČEK Radek. Role of circuit representation in evolutionary design of energy-efficient approximate circuits. IET Computers & Digital Techniques, vol. 2018, no. 4, pp. 139-149. ISSN 1751-8601.
    Detail

    MRÁZEK Vojtěch, VAŠÍČEK Zdeněk, SEKANINA Lukáš, JIANG Honglan and HAN Jie. Scalable Construction of Approximate Multipliers with Formally Guaranteed Worst-Case Error. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 11, pp. 2572-2576. ISSN 1063-8210.
    Detail

  • 2017

    SHAFIQUE Muhammad, HAFIZ Rehan, JAVED Muhammad Usama, ABBAS Sarmad, SEKANINA Lukáš, VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. In: 2017 IEEE Computer Society Annual Symposium on VLSI. Los Alamitos: IEEE Computer Society Press, 2017, pp. 627-632. ISBN 978-1-5090-6762-6.
    Detail

    SEKANINA Lukáš, VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Approximate Circuits in Low-Power Image and Video Processing: The Approximate Median Filter. Radioengineering, vol. 26, no. 3, pp. 623-632. ISSN 1210-2512.
    Detail

    ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished. In: Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD). Irvine, CA: Institute of Electrical and Electronics Engineers, 2017, pp. 416-423. ISBN 978-1-5386-3093-8.
    Detail

    MRÁZEK Vojtěch, HRBÁČEK Radek, VAŠÍČEK Zdeněk and SEKANINA Lukáš. EvoApprox8b: Library of Approximate Adders and Multipliers for Circuit Design and Benchmarking of Approximation Methods. In: Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017, pp. 258-261. ISBN 978-3-9815370-9-3.
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    MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Parallel Optimization of Transistor Level Circuits using Cartesian Genetic Programming. In: GECCO Companion '17 Proceedings of the Companion Publication of the 2017 on Genetic and Evolutionary Computation Conference. Berlin: Association for Computing Machinery, 2017, pp. 1849-1856. ISBN 978-1-4503-4939-0.
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    VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Towards Low Power Approximate DCT Architecture for HEVC Standard. In: Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017, pp. 1576-1581. ISBN 978-3-9815370-9-3.
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    VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Trading between Quality and Non-functional Properties of Median Filter in Embedded Systems. Genetic Programming and Evolvable Machines, vol. 18, no. 1, pp. 45-82. ISSN 1389-2576.
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  • 2016

    HRBÁČEK Radek, MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Automatic Design of Approximate Circuits by Means of Multi-Objective Evolutionary Algorithms. In: Proceedings of the 11th International Conference on Design & Technology of Integrated Systems in Nanoscale Era. Istanbul: Istanbul Sehir University, 2016, pp. 239-244. ISBN 978-1-5090-0335-8.
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    MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Automatic Design of Arbitrary-Size Approximate Sorting Networks with Error Guarantee. In: Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016 26rd International Workshop on. Bremen: Institute of Electrical and Electronics Engineers, 2016, pp. 221-228. ISBN 978-1-5090-0733-2.
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    MRÁZEK Vojtěch, SARWAR Syed Shakib, SEKANINA Lukáš, VAŠÍČEK Zdeněk and ROY Kaushik. Design of Power-Efficient Approximate Multipliers for Approximate Artificial Neural Networks. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Austin, TX: Association for Computing Machinery, 2016, pp. 811-817. ISBN 978-1-4503-4466-1.
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    MRÁZEK Vojtěch. Evoluční snižování příkonu: Od obvodů na úrovni tranzistorů po neuronové sítě na čipu. In: Počítačové architektury a diagnostika PAD 2016. Bořetice: Faculty of Information Technology BUT, 2016, pp. 61-64. ISBN 978-80-214-5376-0.
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    NEVORAL Jan, RŮŽIČKA Richard and MRÁZEK Vojtěch. Evolutionary Design of Polymorphic Gates Using Ambipolar Transistors. In: 2016 IEEE Symposium Series on Computational Intelligence. Athens: Institute of Electrical and Electronics Engineers, 2016, pp. 1-8. ISBN 978-1-5090-4240-1.
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    VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Evolutionary Functional Approximation of Circuits Implemented into FPGAs. In: 2016 IEEE Symposium Series on Computational Intelligence. Athens: Institute of Electrical and Electronics Engineers, 2016, pp. 1-8. ISBN 978-1-5090-4240-1.
    Detail

  • 2015

    MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. In: Proceedings of 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing. Porto: Institute of Electrical and Electronics Engineers, 2015, pp. 106-113. ISBN 978-1-4673-8299-1.
    Detail

    MRÁZEK Vojtěch. Evoluční návrh nízkopříkonových obvodů. In: Počítačové architektury a diagnostika PAD 2015. Zlín: Faculty of Applied Informatics, Tomas Bata University in Zlín, 2015, pp. 1-6. ISBN 978-80-7454-522-1.
    Detail

    MRÁZEK Vojtěch, VAŠÍČEK Zdeněk and SEKANINA Lukáš. Evolutionary Approximation of Software for Embedded Systems: Median Function. In: GECCO Companion '15 Proceedings of the Companion Publication of the 2015 on Genetic and Evolutionary Computation Conference. ACM. New York: Association for Computing Machinery, 2015, pp. 795-801. ISBN 978-1-4503-3488-4.
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    MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Evolutionary Design of Transistor Level Digital Circuits using Discrete Simulation. In: Genetic Programming, 18th European Conference, EuroGP 2015. LCNS 9025. Berlin: Springer International Publishing, 2015, pp. 66-77. ISBN 978-3-319-16500-4.
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  • 2014

    MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform. In: 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014, pp. 9-16. ISBN 978-1-4799-4480-4.
    Detail

    MRÁZEK Vojtěch. Akcelerace evolučního návrhu digitálních obvodů na úrovni tranzistorů s využitím platformy Zynq. In: Proceedings of the 20th Student Conference, EEICT 2014. Volume 2. Brno: Brno University of Technology, 2014, pp. 229-231. ISBN 978-80-214-4923-7.
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