Result Details
FPGA-based Fault Tolerant Architectures and Their Dependability Analysis
Kaštil Jan, Ing., Ph.D., DCSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
In this presentation, a dependability analysis of fault tolerant architectures implemented into the SRAM-based FPGA with reconfiguration controller are presented. The fault tolerant architectures are based on the redundancy of functional units associated with a concurrent error detection technique which uses the principles of PDR as a recovery mechanism from a fault occurrence caused by Single Event Upsets (SEU). Architectures are tested by injecting soft errors into partial bitstreams in FPGA by an SEU injector and the faults coverage of this architecture is obtained. From faults coverage, the failure rate and repair rate are evaluated. Then, Markov dependability models for fault tolerant architectures are created and it is demonstrated how the reliability and availability parameters can be derived from this model for different configurations of architectures. The presentation will be based mainly on the paper, which was presented at the 15th EUROMICRO DSD 2012.
reliability, dependability, FPGA
In this presentation, a dependability analysis of fault tolerant architectures implemented into the SRAM-based FPGA with reconfiguration controller are presented. The fault tolerant architectures are based on the redundancy of functional units associated with a concurrent error detection technique which uses the principles of PDR as a recovery mechanism from a fault occurrence caused by Single Event Upsets (SEU). Architectures are tested by injecting soft errors into partial bitstreams in FPGA by an SEU injector and the faults coverage of this architecture is obtained. From faults coverage, the failure rate and repair rate are evaluated. Then, Markov dependability models for fault tolerant architectures are created and it is demonstrated how the reliability and availability parameters can be derived from this model for different configurations of architectures. The presentation will be based mainly on the paper, which was presented at the 15th EUROMICRO DSD 2012.
@inproceedings{BUT192863,
author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek}",
title="FPGA-based Fault Tolerant Architectures and Their Dependability Analysis",
booktitle="MEMICS'12 -- 8th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
year="2012",
pages="1--1",
publisher="Faculty of Informatics MU",
address="Brno"
}Mathematical and Engineering Approaches to Developing Reliable and Secure Concurrent and Distributed Computer Systems, GACR, Doktorské granty, GD102/09/H042, start: 2009-01-30, end: 2012-12-31, completed