FPGA-based Fault Tolerant Architectures and Their Dependability Analysis

In this presentation, a dependability analysis of fault tolerant architectures implemented into the SRAM-based FPGA with reconfiguration controller are presented. The fault tolerant architectures are based on the redundancy of functional units associated with a concurrent error detection technique which uses the principles of PDR as a recovery mechanism from a fault occurrence caused by Single Event Upsets (SEU). Architectures are tested by injecting soft errors into partial bitstreams in FPGA by an SEU injector and the faults coverage of this architecture is obtained. From faults coverage, the failure rate and repair rate are evaluated. Then, Markov dependability models for fault tolerant architectures are created and it is demonstrated how the reliability and availability parameters can be derived from this model for different configurations of architectures. The presentation will be based mainly on the paper, which was presented at the 15th EUROMICRO DSD 2012.