Publication Details

Optimum Polymorphic Circuits Synthesis Method

FIŠER Petr and ŠIMEK Václav. Optimum Polymorphic Circuits Synthesis Method. In: 13th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). Taormina: IEEE Circuits and Systems Society, 2018, pp. 1-6. ISBN 978-1-5386-5290-9.
Czech title
Syntéza optimálních polymorfních obvodů
Type
conference paper
Language
english
Authors
Fišer Petr, doc. Ing., Ph.D. (FIT CTU)
Šimek Václav, Ing. (DCSY FIT BUT)
Keywords
Polymorphic circuits, Boolean functions, logic synthesis, SAT.
Abstract
Polymorphic circuits represent a newly emerging computation paradigm, where one hardware structure is capable to  perform two or more different intended functions, depending on instantaneous conditions in the target operating environment. Due to the peculiarity of this paradigm, design of these circuits also calls for a novel approach to logic synthesis procedures. Several attempts to enhance the design of such circuits have already been made, producing highly suboptimal solutions. As an ingenious attempt to set lower bounds on complexity and support designers of sophisticated logic synthesis algorithms, a method with the prospect to facilitate the generation of optimum-size polymorphic circuits is presented in this  paper. The core of the proposed method is based on a purposeful exploitation of formal techniques, comprising SAT and PBO in the first place.
Published
2018
Pages
1-6
Proceedings
13th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
Conference
13th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Taormina, IT
ISBN
978-1-5386-5290-9
Publisher
IEEE Circuits and Systems Society
Place
Taormina, IT
DOI
BibTeX
@INPROCEEDINGS{FITPUB11740,
   author = "Petr Fi\v{s}er and V\'{a}clav \v{S}imek",
   title = "Optimum Polymorphic Circuits Synthesis Method",
   pages = "1--6",
   booktitle = "13th International Conference on Design \& Technology of Integrated Systems in Nanoscale Era (DTIS)",
   year = 2018,
   location = "Taormina, IT",
   publisher = "IEEE Circuits and Systems Society",
   ISBN = "978-1-5386-5290-9",
   doi = "10.1109/DTIS.2018.8368585",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/11740"
}
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