Publication Details

Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis

VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. In: 2024.

Type

conference paper

Language

english

Authors

Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY FIT BUT)
Mrázek Vojtěch, Ing., Ph.D. (DCSY FIT BUT)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY FIT BUT)

Published

2024 (in print)

Conference

Design, Automation and Test in Europe, Valencia, ES

BibTeX

@INPROCEEDINGS{FITPUB13136,
   author = "Zden\v{e}k Va\v{s}\'{i}\v{c}ek and Vojt\v{e}ch Mr\'{a}zek and Luk\'{a}\v{s} Sekanina",
   title = "Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis",
   year = 2024,
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/13136"
}