Publication Details

On Area Minimization of Complex Combinational Circuits Using Cartesian Genetic Programming

VAŠÍČEK Zdeněk and SEKANINA Lukáš. On Area Minimization of Complex Combinational Circuits Using Cartesian Genetic Programming. In: 2012 IEEE World Congress on Computational Intelligence. CA: Institute of Electrical and Electronics Engineers, 2012, pp. 2379-2386. ISBN 978-1-4673-1508-1.
Czech title
K minimalizaci složitějších kombinačních obvodů pomocí kartézského genetického programování
Type
conference paper
Language
english
Authors
Keywords
logic synthesis, optimization, genetic programming, selection
Abstract


The paper deals with the evolutionary post synthesis optimization of complex combinational circuits with the aim of reducing the area on a chip as much as possible. In order to optimize complex circuits, Cartesian Genetic Programming (CGP) is employed where the fitness function is based on a formal equivalence checking algorithm rather than evaluating all possible input assignments. The standard selection strategy of CGP is modified to be more explorative and so agile in very rugged fitness landscapes. It was shown on the LGSynth93 benchmark circuits that the modified selection strategy leads to more compact circuits in roughly 50% cases. The average area improvement is 24% with respect to the results of conventional synthesis. Delay of optimized circuits was also analyzed. 
Published
2012
Pages
2379-2386
Proceedings
2012 IEEE World Congress on Computational Intelligence
Conference
IEEE World Congress on Computational Intelligence, Brisbane, AU
ISBN
978-1-4673-1508-1
Publisher
Institute of Electrical and Electronics Engineers
Place
CA, US
DOI
BibTeX
@INPROCEEDINGS{FITPUB9866,
   author = "Zden\v{e}k Va\v{s}\'{i}\v{c}ek and Luk\'{a}\v{s} Sekanina",
   title = "On Area Minimization of Complex Combinational Circuits Using Cartesian Genetic Programming",
   pages = "2379--2386",
   booktitle = "2012 IEEE World Congress on Computational Intelligence",
   year = 2012,
   location = "CA, US",
   publisher = "Institute of Electrical and Electronics Engineers",
   ISBN = "978-1-4673-1508-1",
   doi = "10.1109/CEC.2012.6256649",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/9866"
}
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