Result Details
Normalized Testability Measures Based on RTL Digital Circuit Graph Model Analysis
STRNADEL, J. Normalized Testability Measures Based on RTL Digital Circuit Graph Model Analysis. Proceedings of The fifth International Scientific Conference Electronic Computers and Informatics 2002. Edition 55. Košice: The University of Technology Košice, 2002. p. 200-205. ISBN: 80-7099-879-2.
Type
conference paper
Language
English
Authors
Strnadel Josef, Ing., Ph.D., FIT (FIT)
Abstract
The paper presents measures for testability valuation of a digital circuit at register-transfer level (RT level, RTL). Definition of a graph model of a RTL digital circuit for these purposes and mathematical formulas of measures for testability valuation based on analysis of proposed graph model are presented in this paper. Finally, experimental results are presented.
Keywords
Register transfer level, digital circuit graph model, testability analysis measures
Published
2002
Pages
200–205
Proceedings
Proceedings of The fifth International Scientific Conference Electronic Computers and Informatics 2002
Series
Edition 55
Conference
Electronic Computers and Informatics'2002
ISBN
80-7099-879-2
Publisher
The University of Technology Košice
Place
Košice
BibTeX
@inproceedings{BUT10247,
author="Josef {Strnadel}",
title="Normalized Testability Measures Based on RTL Digital Circuit Graph Model Analysis",
booktitle="Proceedings of The fifth International Scientific Conference Electronic Computers and Informatics 2002",
year="2002",
series="Edition 55",
pages="200--205",
publisher="The University of Technology Košice",
address="Košice",
isbn="80-7099-879-2",
url="https://www.fit.vut.cz/research/publication/6995/"
}
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