Result Details

Instructor Selector Generation from Architecture Description

TRMAČ, M.; HUSÁR, A.; HRANÁČ, J.; HRUŠKA, T.; MASAŘÍK, K. Instructor Selector Generation from Architecture Description. 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2010. p. 167-174. ISBN: 978-80-87342-10-7.
Type
conference paper
Language
English
Authors
Trmač Miloslav, Mgr., FIT (FIT)
Husár Adam, Ing., Ph.D., FIT (FIT), DIFS (FIT)
Hranáč Jan, Ing.
Hruška Tomáš, prof. Ing., CSc., DIFS (FIT)
Masařík Karel, Ing., Ph.D., FIT (FIT), DIFS (FIT)
Abstract

We describe an automated way to generate data for a practical LLVM instruction selector based on machine-generated description of the target architecture at register transfer level.

The generated instruction selector can handle arbitrarily complex machine instructions with no internal control flow, and can automatically find and take advantage of arithmetic properties of an instructions, specialized
pseudo-registers and special cases of immediate operands.

Keywords

compiler, instruction selection, LLVM, ISAC

Published
2010
Pages
167–174
Proceedings
6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
Conference
MEMICS'10 -- 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
ISBN
978-80-87342-10-7
Publisher
Masaryk University
Place
Brno
BibTeX 
@inproceedings{BUT37045,
  author="Miloslav {Trmač} and Adam {Husár} and Jan {Hranáč} and Tomáš {Hruška} and Karel {Masařík}",
  title="Instructor Selector Generation from Architecture Description",
  booktitle="6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2010",
  pages="167--174",
  publisher="Masaryk University",
  address="Brno",
  isbn="978-80-87342-10-7"
}
Projects
National Support for Project Smart Multicore Embedded SYstems, MŠMT, Společné technologické iniciativy, 7H10014, start: 2010-02-01, end: 2013-01-31, running
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
System for Programming and Realization of Embedded Systems, MPO, TIP, FR-TI1/038, start: 2009-07-01, end: 2013-06-30, completed
Research groups
Hardware-Software Codesign research group (RG LISSOM)
Departments
Department of Information Systems (DIFS)
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