Result Details

Approximate Circuit Design by Means of Evolvable Hardware

SEKANINA, L.; VAŠÍČEK, Z. Approximate Circuit Design by Means of Evolvable Hardware. In 2013 IEEE International Conference on Evolvable Systems (ICES). Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI). Singapur: IEEE Computer Society, 2013. p. 21-28. ISBN: 978-1-4673-5847-7.
Type
conference paper
Language
English
Authors
Sekanina Lukáš, prof. Ing., Ph.D., DCSY (FIT)
Vašíček Zdeněk, doc. Ing., Ph.D., DCSY (FIT)
Abstract


This paper deals with evolutionary design of approximate
circuits. This class of circuits is characterized by relaxing the requirement on functional equivalence between the specification and implementation in order to reduce the area on a chip or minimize energy consumption. We proposed a CGP-based automated design method which enables to find a good trade off between key circuit parameters (functionality, area and power consumption). In particular, the digital approximate circuits consisting of elementary gates are addressed in this paper. Experimental results are provided for combinational single-output circuits and adders where two different metrics are compared for the error assessment.

Keywords


approximate circuit, evolutionary design, multiplier, adder

Published
2013
Pages
21–28
Proceedings
2013 IEEE International Conference on Evolvable Systems (ICES)
Series
Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI)
Conference
2013 IEEE International Conference on Evolvable Systems - From Biology to Hardware
ISBN
978-1-4673-5847-7
Publisher
IEEE Computer Society
Place
Singapur
DOI
10.1109/ICES.2013.6613278
EID Scopus
2-s2.0-84886663174
BibTeX 
@inproceedings{BUT103438,
  author="Lukáš {Sekanina} and Zdeněk {Vašíček}",
  title="Approximate Circuit Design by Means of Evolvable Hardware",
  booktitle="2013 IEEE International Conference on Evolvable Systems (ICES)",
  year="2013",
  series="Proceedings of the 2013 IEEE Symposium Series on Computational Intelligence (SSCI)",
  pages="21--28",
  publisher="IEEE Computer Society",
  address="Singapur",
  doi="10.1109/ICES.2013.6613278",
  isbn="978-1-4673-5847-7",
  url="https://www.fit.vut.cz/research/publication/10198/"
}
Files
Projects
Advanced secured, reliable and adaptive IT, BUT, Vnitřní projekty VUT, FIT-S-11-1, start: 2011-01-01, end: 2013-12-31, completed
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, start: 2011-01-01, end: 2015-12-31, completed
Natural Computing on Unconventional Platforms, GACR, Standardní projekty, GAP103/10/1517, start: 2010-01-01, end: 2013-12-31, running
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
Departments
Department of Computer Systems (DCSY)
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