Result Details

Generic Partial Dynamic Reconfiguration Controller for Transient and Permanent Fault Mitigation in Fault Tolerant Systems Implemented Into FPGA

KOTÁSEK, Z.; MIČULKA, L. Generic Partial Dynamic Reconfiguration Controller for Transient and Permanent Fault Mitigation in Fault Tolerant Systems Implemented Into FPGA. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014. p. 171-174. ISBN: 978-0-7695-5074-9.

Type

conference paper

Language

English

Authors

Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
Mičulka Lukáš, Ing., Ph.D.

Abstract

This paper presents a small flexible reconfiguration controller for driving the reconfiguration process after transient or permanent fault attack based on techniques described in our methodology. The basic architecture together with the implementation and synthesis results and comparison with other solution are demonstrated.

Keywords

reconfiguration controller, partial dynamic reconfiguration, relocation, synchronization, limited redundant space

Published

2014

Pages

171–174

Proceedings

17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

Conference

IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2014

ISBN

978-0-7695-5074-9

Publisher

IEEE Computer Society

Place

Warszawa

DOI

10.1109/DDECS.2014.6868784

UT WoS

000346734200034

EID Scopus

2-s2.0-84924061699

BibTeX

@inproceedings{BUT111542,
  author="Zdeněk {Kotásek} and Lukáš {Mičulka}",
  title="Generic Partial Dynamic Reconfiguration Controller for Transient and Permanent Fault Mitigation in Fault Tolerant Systems Implemented Into FPGA",
  booktitle="17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems",
  year="2014",
  pages="171--174",
  publisher="IEEE Computer Society",
  address="Warszawa",
  doi="10.1109/DDECS.2014.6868784",
  isbn="978-0-7695-5074-9"
}

Projects

Architektury paralelních a vestavěných počítačových systémů, BUT, Vnitřní projekty VUT, FIT-S-14-2297, start: 2014-01-01, end: 2016-12-31, completed
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, start: 2011-01-01, end: 2015-12-31, completed
Manufacturable and Dependable Multicore Architectures at Nanoscale, MŠMT, COST, COST IC1103, start: 2011-06-15, end: 2015-12-31, completed
Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification, MŠMT, COST CZ (2011-2017), LD12036, start: 2012-03-01, end: 2015-11-30, completed

Research groups

Dependable Digital Systems Research Group (RG DEPSYS)

Departments

Department of Computer Systems (DCSY)