Result Details

Automation and Optimization of Coverage-driven Verification

ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Automation and Optimization of Coverage-driven Verification. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015. p. 87-94. ISBN: 978-1-4673-8035-5.
Type
conference paper
Language
English
Authors
Zachariášová Marcela, Ing., Ph.D., DCSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
Abstract


This paper proposes a new method for automation
and optimization of coverage-driven verification (CDV) of
hardware systems that is based on evolutionary computing. In
comparison with the standard CDV that utilizes random search,
using this method, the convergence to the maximum coverage
is much faster, fewer input stimuli are used and no manual
effort is required from the user. Moreover, the optimization is
targeted to the verification process itself without the dependence
on the circuit that is verified. For the demonstration purposes, the
sequential arithmetic-logic unit (ALU) and the RISC processor
were verified and the results show that using the optimization
method, a significant improvement can be achieved.

Keywords

functional verification
automation
optimization
genetic algorithm

Published
2015
Pages
87–94
Proceedings
Proceedings of the 18th Euromicro Conference on Digital Systems Design
Conference
18th Euromicro Conference on Digital Systems Design
ISBN
978-1-4673-8035-5
Publisher
IEEE Computer Society
Place
Funchal
DOI
10.1109/DSD.2015.34
UT WoS
000382382300012
EID Scopus
2-s2.0-84958158712
BibTeX 
@inproceedings{BUT119894,
  author="Marcela {Zachariášová} and Zdeněk {Kotásek}",
  title="Automation and Optimization of Coverage-driven Verification",
  booktitle="Proceedings of the 18th Euromicro Conference on Digital Systems Design",
  year="2015",
  pages="87--94",
  publisher="IEEE Computer Society",
  address="Funchal",
  doi="10.1109/DSD.2015.34",
  isbn="978-1-4673-8035-5"
}
Projects
Architektury paralelních a vestavěných počítačových systémů, BUT, Vnitřní projekty VUT, FIT-S-14-2297, start: 2014-01-01, end: 2016-12-31, completed
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, start: 2011-01-01, end: 2015-12-31, completed
Manufacturable and Dependable Multicore Architectures at Nanoscale, MŠMT, COST, COST IC1103, start: 2011-06-15, end: 2015-12-31, completed
Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification, MŠMT, COST CZ (2011-2017), LD12036, start: 2012-03-01, end: 2015-11-30, completed
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Computer Systems (DCSY)
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