Result Details
A Pipeline Scheduling Algorithm for High-Level Synthesis
Scheduling is the most important task in high-level synthesis process,while pipelining is highly important for realising high-performancedigital components. This paper presents a pipeline list-basedscheduling algorithm, which performs forward and backward pipelining.The forward priority function is based on incorporating someinformation extracted from data flow graph (DFG) structure to guide thescheduler to find near-optimal/optimal schedules quickly. The algorithmhas a flexible procedure cycle, which allows designers to makeefficient area-performance trade-offs by using different strategiesemployed. Designers can choose between doing forward / backwardpipelining with or without resource sharing combined with clock cycleselection, pipe stage delay determination. Experimental results withstandard benchmarks show the effectiveness of the proposed algorithm.
pipelines, algorithms, synthesis, architecture, computer-aided design.
@inproceedings{BUT13786,
author="Azeddien {Sllame M.}",
title="A Pipeline Scheduling Algorithm for High-Level Synthesis",
booktitle="Proc. of IFAC Workshop on Programmable Devices and Systems Conference",
year="2003",
pages="178--183",
publisher="Elsevier Science",
address="Ostrava",
isbn="0-08-044130-0"
}