On the Automatic Design of Testable Circuits

Type

conference paper

Language

English

Authors

Sekanina Lukáš, prof. Ing., Ph.D.
Růžička Richard, doc. Ing., Ph.D., MBA

Abstract

An approach to the design of non-trivial circuits that are competitive with conventional designs in terms of quality as well as implementation cost, and furthermore, which are easily testable, is introduced in this paper.

Keywords

Evolutionary design, testability, digital circuits

Annotation

An approach to the design of non-trivial circuits that are competitive with conventional designs in terms of quality as well as implementation cost, and furthermore, which are easily testable, is introduced in this paper.

Published

2003

Pages

299–300

Proceedings

Proceedings of IEEE Workshop on Design nad Diagnostics of Electronic Circuits and Systems

Conference

6th IEEE International Workshop On DDECS

ISBN

83-7143-557-6

Publisher

Publishing House of Poznan University of Technology

Place

Poznań

BibTeX

@inproceedings{BUT13960,
  author="Lukáš {Sekanina} and Richard {Růžička}",
  title="On the Automatic Design of Testable Circuits",
  booktitle="Proceedings of IEEE Workshop on Design nad Diagnostics of Electronic Circuits and Systems",
  year="2003",
  pages="299--300",
  publisher="Publishing House of Poznan University of Technology",
  address="Poznań",
  isbn="83-7143-557-6"
}

Projects

Formal approach to digital circuits test scheduling, GACR, Postdoktorandské granty, GP102/03/P176, start: 2003-01-01, end: 2005-12-31, completed
Formal Approaches in Digital Design Diagnostics - Testable Design Verification, GACR, Standardní projekty, GA102/01/1531, start: 2001-01-01, end: 2003-12-31, completed

Research groups

Supercomputing Technologies Research Group SC@FIT (RG SC@FIT)

Departments

Faculty of Information Technology (FIT)