Result Details

A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation

LOJDA, J.; KOTÁSEK, Z. A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation. Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017. p. 79-80. ISBN: 978-80-01-06178-7.
Type
conference paper
Language
English
Authors
Lojda Jakub, Ing., Ph.D., DCSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
Abstract

In this presentation, an approach to fault-tolerant systems design and synthesis based onHigh-level Synthesis (HLS) is shown. A description and evaluation of the impacts of HLS optimizationmethods are shown as well. The higher reliability is achieved through modificationof input description in the C++ programming language, which the HLS synthesistools are based on. Our work targets SRAM-based FPGAs, which are prone toSingle Event Upsets (SEUs). For the evaluation of the impacts of faults we use our evaluation platform, which allows us to test fault toleranceproperties of the Design Under Test (DUT). The evaluation platform is based onfunctional verification combined with fault injection.

Keywords

High-level Synthesis, Data-Path, CatapultC, Fault Tolerance, Fault-Tolerant, Robot Controller, C++

Published
2017
Pages
79–80
Proceedings
Proceedings of the 5th Prague Embedded Systems Workshop
Conference
The 5th Prague Embedded Systems Workshop
ISBN
978-80-01-06178-7
Publisher
Faculty of Information Technology, Czech Technical University
Place
Roztoky u Prahy
BibTeX 
@inproceedings{BUT144442,
  author="Jakub {Lojda} and Zdeněk {Kotásek}",
  title="A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation",
  booktitle="Proceedings of the 5th Prague Embedded Systems Workshop",
  year="2017",
  pages="79--80",
  publisher="Faculty of Information Technology, Czech Technical University",
  address="Roztoky u Prahy",
  isbn="978-80-01-06178-7",
  url="https://www.fit.vut.cz/research/publication/11451/"
}
Files
Projects
Algorithms, Design Methods, and Many-Core Execution Platform for Low-Power Massive Data-Rate Video and Image Processing, MŠMT, Společné technologické iniciativy, 7H14002, start: 2014-04-01, end: 2017-06-30, completed
IT4Innovations excellence in science, MŠMT, Národní program udržitelnosti II, LQ1602, start: 2016-01-01, end: 2020-12-31, completed
Pokročilé paralelní a vestavěné počítačové systémy, BUT, Vnitřní projekty VUT, FIT-S-17-3994, start: 2017-03-01, end: 2020-02-29, completed
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Computer Systems (DCSY)
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