Result Details
Mapping of P4 Match Action Tables to FPGA
KEKELY, M.; KOŘENEK, J. Mapping of P4 Match Action Tables to FPGA. In Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS. Ghent: Institute of Electrical and Electronics Engineers, 2017. p. 1-2. ISBN: 978-90-90-30428-1.
Type
conference paper
Language
English
Authors
Kekely Michal, Ing., Ph.D., DCSY (FIT)
Kořenek Jan, doc. Ing., Ph.D., DCSY (FIT)
Kořenek Jan, doc. Ing., Ph.D., DCSY (FIT)
Abstract
Current networks are changing very fast. Network
administrators need
more flexible and powerful tools to be able to
support new protocols or services very fast. The P4 language
provides new level of abstraction for flexible packet processing.
Therefore, we have designed new architecture for memory
efficient mapping of P4 match/action tables to FPGA. The architecture is based on DCFL algorithm and is able to balance
the processing speed and available memory resources.
support new protocols or services very fast. The P4 language
provides new level of abstraction for flexible packet processing.
Therefore, we have designed new architecture for memory
efficient mapping of P4 match/action tables to FPGA. The architecture is based on DCFL algorithm and is able to balance
the processing speed and available memory resources.
Keywords
P4, FPGA, packet classification, match action tables
Published
2017
Pages
1–2
Proceedings
Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS
Conference
27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS
ISBN
978-90-90-30428-1
Publisher
Institute of Electrical and Electronics Engineers
Place
Ghent
DOI
UT WoS
000426989400013
EID Scopus
BibTeX
@inproceedings{BUT144482,
author="Michal {Kekely} and Jan {Kořenek}",
title="Mapping of P4 Match Action Tables to FPGA",
booktitle="Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS",
year="2017",
pages="1--2",
publisher="Institute of Electrical and Electronics Engineers",
address="Ghent",
doi="10.23919/FPL.2017.8056768",
isbn="978-90-90-30428-1"
}
Projects
Pokročilé paralelní a vestavěné počítačové systémy, BUT, Vnitřní projekty VUT, FIT-S-17-3994, start: 2017-03-01, end: 2020-02-29, completed
Smart Application Aware Embedded Probes, MV, Bezpečnostní výzkum České republiky 2015-2020, VI20152019001, start: 2015-09-01, end: 2019-05-31, completed
Smart Application Aware Embedded Probes, MV, Bezpečnostní výzkum České republiky 2015-2020, VI20152019001, start: 2015-09-01, end: 2019-05-31, completed
Departments