Result Details

Hardware Router's Lookup Machine and its Formal Verification

ANTOŠ, D.; KOŘENEK, J. Hardware Router's Lookup Machine and its Formal Verification. Proceedings of the 3rd International Conference on Networking ICN '04. Colmar: University of Haute Alsace, 2004. p. 1002-1007. ISBN: 0-86341-325-0.
Type
conference paper
Language
English
Authors
Antoš David, Mgr.
Kořenek Jan, doc. Ing., Ph.D., DCSY (FIT)
Abstract

This article describes the design of the lookup machine implemented inhardware accelerator COMBO6 for IPv6 and IPv4 packet routing. The lookupmachine is a single instruction machine using Content Addressable andStatic Memories and the operations are performed by Field ProgrammableGate Arrays.The design of the lookup machine is difficult to be proven correct byconventional methods, therefore model checking as a method of formalverification was employed and this case is explained in detail.In the last part, the article sums up software support needed to makebehavior of the accelerator equivalent to the host computer.

Keywords

IPv6 routing, FPGA, formal verification, Liberouter

Published
2004
Pages
1002–1007
Proceedings
Proceedings of the 3rd International Conference on Networking ICN '04
Conference
3rd International Conference on Networking
ISBN
0-86341-325-0
Publisher
University of Haute Alsace
Place
Colmar
BibTeX 
@inproceedings{BUT17149,
  author="David {Antoš} and Jan {Kořenek}",
  title="Hardware Router's Lookup Machine and its Formal Verification",
  booktitle="Proceedings of the 3rd International Conference on Networking ICN '04",
  year="2004",
  pages="1002--1007",
  publisher="University of Haute Alsace",
  address="Colmar",
  isbn="0-86341-325-0"
}
Projects
Optická síť národního výzkumu a její nové aplikace, MŠMT, Výzkumná centra (2000-2004), MSM6383917201, start: 2004-01-01, end: 2010-12-31, completed
Research groups
Reconfigurable Architecture Research Group (VZ FPGA)
Departments
Department of Computer Systems (DCSY)
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