Result Details

Design of the Special Fast Reconfigurable Chip Using Common FPGA

SEKANINA, L.; RŮŽIČKA, R. Design of the Special Fast Reconfigurable Chip Using Common FPGA. Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000. Smolenice: unknown, 2000. p. 161-168. ISBN: 80-968320-3-4.
Type
conference paper
Language
English
Authors
Sekanina Lukáš, prof. Ing., Ph.D.
Růžička Richard, doc. Ing., Ph.D., MBA
Abstract

Some applications require chips with fast partial reconfiguration. These requirements are traditionally satisfied by a special chip design, but it is usually a very expensive solution. This paper describes a new approach. Special fast partially reconfigurable chip is implemented with a common FPGA. The format of the configuration bit stream is suggested and optimized according to the given task. Result chip offers many good properties, but some problems with scalability can appear.

Keywords

reconfigurable circuits, evolvable hardware

URL
Annotation
Published
2000
Pages
161–168
Proceedings
Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000
Conference
Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000
ISBN
80-968320-3-4
Publisher
unknown
Place
Smolenice
BibTeX 
@inproceedings{BUT17637,
  author="Lukáš {Sekanina} and Richard {Růžička}",
  title="Design of the Special Fast Reconfigurable Chip Using Common FPGA",
  booktitle="Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000",
  year="2000",
  pages="161--168",
  publisher="unknown",
  address="Smolenice",
  isbn="80-968320-3-4",
  url="http://www.fit.vutbr.cz/~sekanina/publ/ddecs00/rechip.pdf"
}
Projects
Methodology and tools for digital circuits testability analysis, GACR, Standardní projekty, GA102/98/1463, start: 1998-01-01, end: 2006-03-31, completed
Research groups
Evolvable Hardware Research Group (RG EHW)
Supercomputing Technologies Research Group SC@FIT (RG SC@FIT)
Departments
Faculty of Information Technology (FIT)
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