Result Details

Generating Synthetic Benchmark Circuits with Predefined Testability Properties

PEČENKA, T. Generating Synthetic Benchmark Circuits with Predefined Testability Properties. Pre-Proc. 1st Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: 2005. p. 200-209.
Type
conference paper
Language
English
Authors
Pečenka Tomáš, Ing., Ph.D., DCSY (FIT)
Abstract

The paper describes the utilization of evolutionary algorithms for automatic discovery of benchmark circuits. The main objective of the paper is to show that relatively large and complex (benchmark) circuits  with predefined testability properties can be evolved in case that only a given property (e.g. testability) is required and the function of the circuit is
not considered. Fitness evaluation for the proposed algorithm is based on testability analy\-sis with linear time complexity.  During the evolution, the solutions which are refused to be synthesized by a design system are excluded from the process of developing a new generation of benchmark circuits.  The fulfilment of testability properties of generated circuits was verified by professional ATPG (Automated Test Pattern Generation) tool.

Keywords

benchmark circuits, evolutionary design

Published
2005
Pages
200–209
Proceedings
Pre-Proc. 1st Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
Conference
1st Doctoral Workshop on Mathematical and Engineering Methods in Computer Science -- MEMICS 2005
Place
Brno
BibTeX
@inproceedings{BUT18278,
  author="Tomáš {Pečenka}",
  title="Generating Synthetic Benchmark Circuits with Predefined Testability Properties",
  booktitle="Pre-Proc. 1st Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2005",
  pages="200--209",
  address="Brno"
}
Projects
Integrated approach to education of PhD students in the area of parallel and distributed systems, GACR, Doktorské granty, GD102/05/H050, start: 2005-01-01, end: 2008-12-31, completed
Research groups
Departments
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