Result Details
A Novel 10-bit, 40 MHz, 54 mW Pipelined ADC
Vrba Radimír, prof. Ing., CSc., UMEL (FEEC)
The article describes a new background calibration technique, which is used in a new 10-bit low power pipelined ADC. The switched-capacitor approach (SC) is utilized in proposed ADC as well. The low power consumption is one of the most important issues considered in the design, because the ADC is intended for using in portable applications. Well-known operational-amplifier (op-amp) sharing technique was modified and used to decrease the power usage. The capacitor scaling approach is suitable for the same purpose. The basic problems coupled to SC, such as clock feedthrough from digital part through the switches, capacitor mismatch and op-amp non-idealities, have been taken into account during a design of the ADC. These error sources are canceled or roughly attenuated by means of novel background calibration or using known analog-domain techniques. The special op-amps and comparators were designed for this purpose. The power consumption of the op-amps was taken into account, too.
Pipelined ADC, switched-capacitors, background calibration, portable devices
@inproceedings{BUT18555,
author="Jiří {Háze} and Radimír {Vrba}",
title="A Novel 10-bit, 40 MHz, 54 mW Pipelined ADC",
booktitle="ISCCSP Proceedings 2006",
year="2006",
number="1",
pages="4",
publisher="IEEE CAS",
address="Marrakech, Maroko",
isbn="2-908849-17-8"
}