Formal Approach to RTL Testability Analysis

In the paper a formal approach to the RT level testability analysis ispresented. It is based on the structural analysis of the circuit underdesign and the classification of circuit elements. The elements areclassified on the basis of their possible role during the testapplication. The principles known from the theory of sets andmathematical logic are utilised to define the role of registers duringthe test application. The principles of developing the RT leveltestability analysis algorithms are then presented to identifyregisters for partial scan and parallel paths to apply the test of thecircuit.