Result Details
Decreasing Test Time by Scan Chain Reorganization
Abstract of the same name paper presented on DDECS Symposium 2011.
In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. The principles of the
methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. The methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.
scan chain, test, time, reordering, reorganization, physical, layout
@misc{BUT192746,
author="Pavel {Bartoš} and Zdeněk {Kotásek} and Jan {Dohnal}",
title="Decreasing Test Time by Scan Chain Reorganization",
booktitle="7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
year="2011",
pages="108--108",
publisher="Brno University of Technology",
address="Brno",
isbn="978-80-214-4305-1",
note="Abstract"
}Mathematical and Engineering Approaches to Developing Reliable and Secure Concurrent and Distributed Computer Systems, GACR, Doktorské granty, GD102/09/H042, start: 2009-01-30, end: 2012-12-31, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
SoC circuits reliability and availability improvement, GACR, Standardní projekty, GA102/09/1668, start: 2009-01-01, end: 2011-12-31, completed