Result Details

VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements

STRNADEL, J. VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements. Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005. p. 190-193. ISBN: 963-9364-48-7.
Type
conference paper
Language
English
Authors
Strnadel Josef, Ing., Ph.D., DCSY (FIT)
Abstract

The work deals with testability analysis of data-path within register-transfer level digital circuits and with utilizing its results in selected areas in digital circuit diagnostics area. In the work, it is shown that it is advantageous if each module stored in a design library is equipped both with design-related information and special diagnostics-related information usable for testability-analysis purposes in our case. During our research, such information was described by means of a formal mathematical model based on so-called transparency conception. Proposed digraph-search based testability analysis method is described by means of instruments specified in the model.

Keywords

Testability analysis, data-path, register-transfer level, transparency, I-path concept, virtual port, digraph, test-pattern data-flow digraph, test-response data-flow digraph, graph algorithm, design for testability, scan, benchmark circuit.

Published
2005
Pages
190–193
Proceedings
Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop
Conference
IEEE Design and Diagnostics of Electronic Circuits and systems (DDECS'06)
The 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
ISBN
963-9364-48-7
Publisher
University of West Hungary
Place
Sopron
BibTeX 
@inproceedings{BUT21464,
  author="Josef {Strnadel}",
  title="VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements",
  booktitle="Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop",
  year="2005",
  pages="190--193",
  publisher="University of West Hungary",
  address="Sopron",
  isbn="963-9364-48-7",
  url="https://www.fit.vut.cz/research/publication/7745/"
}
Files
Projects
Modern Methods of Digital Systems Design, GACR, Standardní projekty, GA102/04/0737, start: 2004-01-01, end: 2006-12-31, completed
Optimizing Methods in Digital Systems Diagnosis, GACR, Postdoktorandské granty, GP102/05/P193, start: 2005-01-01, end: 2007-12-31, completed
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Computer Systems (DCSY)
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