Result Details
High Availability Fault Tolerant Architectures Implemented into FPGAs
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
In the paper, the methodology of fault tolerant systems design based on FPGA are presented. The architectures are based both on duplex and TMR systems to which fault detection capabilities are added, the use of on-line checkers for this purpose is demonstrated. It is described how reliability and availability parameters in TMR and duplex structures with checkers can be increased. To demonstrate this, analytical calculations based on Markov reliability model are used. It is also shown how the availability parameters can be affected by the operating environment into which the fault tolerant system is implemented. The principles of generating sequence of FT architectures with different level of diagnostic are presented.
TMR, availability, Markov reliability model, FPGA, fault tolerant systems, checker
@inproceedings{BUT30207,
author="Martin {Straka} and Zdeněk {Kotásek}",
title="High Availability Fault Tolerant Architectures Implemented into FPGAs",
booktitle="12th EUROMICRO Conference on Digital System Design DSD 2009",
year="2009",
pages="108--116",
publisher="IEEE Computer Society",
address="Patras",
isbn="978-0-7695-3782-5"
}Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
SoC circuits reliability and availability improvement, GACR, Standardní projekty, GA102/09/1668, start: 2009-01-01, end: 2011-12-31, completed