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Transistor-level Evolution of Digital Circuits Using a Special Circuit Simulator

ŽALOUDEK, L.; SEKANINA, L. Transistor-level Evolution of Digital Circuits Using a Special Circuit Simulator. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. p. 320-331. ISBN: 978-3-540-85856-0.
Type
conference paper
Language
English
Authors
Abstract

An evolutionary algorithm is used to design digital circuits at the transistor level. In particular, various static CMOS circuits with up to four inputs were evolved. The increase in the complexity of evolved circuits wrt existing circuits evolved at the transistor level is primarily caused by two phenomena: the usage of a specialized circuit simulator and restriction of the search space. Because we restricted the search space to the set of  "reasonable designs" we could employ imperfect, but very fast circuit simulation. The usage of proposed simulator allowed exploring more candidate designs than a conventional Spice-based approach. However, in some cases, an incorrect behavior was detected after validation of evolved circuits using Spice simulator.

Keywords

evolutionary design, digital circuit, transistor-level design

Published
2008
Pages
320–331
Proceedings
Evolvable Systems: From Biology to Hardware
Series
Lecture Notes in Computer Science
Volume
5216
Conference
Evolvable Systems: From Biology to Hardware
ISBN
978-3-540-85856-0
Publisher
Springer Verlag
Place
Berlin
BibTeX
@inproceedings{BUT30755,
  author="Luděk {Žaloudek} and Lukáš {Sekanina}",
  title="Transistor-level Evolution of Digital Circuits Using a Special Circuit Simulator",
  booktitle="Evolvable Systems: From Biology to Hardware",
  year="2008",
  series="Lecture Notes in Computer Science",
  volume="5216",
  pages="320--331",
  publisher="Springer Verlag",
  address="Berlin",
  isbn="978-3-540-85856-0",
  url="https://www.fit.vut.cz/research/publication/8665/"
}
Files
Projects
Methods of polymorphic digital circuit design, GACR, Standardní projekty, GA102/06/0599, start: 2006-01-01, end: 2008-12-31, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
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