Result Details

Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming

GAJDA, Z.; SEKANINA, L. Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming. Proc. of 2009 IEEE Congress on Evolutionary Computation. NA: IEEE Computational Intelligence Society, 2009. p. 1599-1604. ISBN: 978-1-4244-2958-5.
Type
conference paper
Language
English
Authors
Gajda Zbyšek, Ing., Ph.D., DCSY (FIT)
Sekanina Lukáš, prof. Ing., Ph.D., DCSY (FIT)
Abstract

Polymorphic digital circuits contain ordinary and polymorphic gates. In the past, Cartesian Genetic Programming (CGP) has been applied to synthesize polymorphic circuits at the gate level. However, this approach is not scalable. Experimental results presented in this paper indicate that larger and more efficient polymorphic circuits can be designed by a combination of conventional design methods and evolutionary optimization (conducted by CGP). Proposed methods are evaluated on two benchmark circuits of variable input size.

Keywords

polymorphic circuit, circuit synthesis, evolutionary design, cartesian genetic programming

Published
2009
Pages
1599–1604
Proceedings
Proc. of 2009 IEEE Congress on Evolutionary Computation
Conference
IEEE Congress on Evolutionary Computation
ISBN
978-1-4244-2958-5
Publisher
IEEE Computational Intelligence Society
Place
NA
BibTeX 
@inproceedings{BUT33725,
  author="Zbyšek {Gajda} and Lukáš {Sekanina}",
  title="Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming",
  booktitle="Proc. of 2009 IEEE Congress on Evolutionary Computation",
  year="2009",
  pages="1599--1604",
  publisher="IEEE Computational Intelligence Society",
  address="NA",
  isbn="978-1-4244-2958-5",
  url="https://www.fit.vut.cz/research/publication/8949/"
}
Files
Projects
Methods of polymorphic digital circuit design, GACR, Standardní projekty, GA102/06/0599, start: 2006-01-01, end: 2008-12-31, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
Research groups
Evolvable Hardware Research Group (RG EHW)
Departments
Department of Computer Systems (DCSY)
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