Result Details
Reliability Models for Fault Tolerant Architectures Based on FPGA
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
In this presentation, a methodology of FTS design based on FPGA is
presented. The FT architectures are based both on duplex and TMR
systems to which fault detection capabilities are added, the use
of on-line checkers for this purpose is demonstrated. It is
described how reliability and availability parameters in TMR and
duplex structures with checkers can be increased. To demonstrate
this, analytical calculations based on Markov reliability model
are used. It is also shown how the availability parameters can be
affected by the operating environment into which the FTS is
implemented. Finally, the results of research and the comparison
of our approach with classical TMR and duplex architectures for
different failure rates are presented.
TMR, checker, fault tolerant system, reliability model, availability, FPGA
@inproceedings{BUT33747,
author="Martin {Straka} and Zdeněk {Kotásek}",
title="Reliability Models for Fault Tolerant Architectures Based on FPGA",
booktitle="5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
year="2009",
pages="239--239",
publisher="Faculty of Informatics MU",
address="Brno",
isbn="978-80-87342-04-6"
}Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running