Result Details

Efficient Hardware Accelerator for Symbolic Regression Problems

VAŠÍČEK, Z.; SEKANINA, L. Efficient Hardware Accelerator for Symbolic Regression Problems. 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2009. p. 192-199. ISBN: 978-80-87342-04-6.

Type

conference paper

Language

English

Authors

Vašíček Zdeněk, doc. Ing., Ph.D., CIS - Internal Systems (CIS), DCSY (FIT)
Sekanina Lukáš, prof. Ing., Ph.D., DCSY (FIT)

Abstract

In this paper, a new hardware architecture for the acceleration of symbolic regression problems using Cartesian Genetic Programming (CGP) is presented.
In order to minimize the number of expensive memory accesses, a new algorithm is proposed.
The search algorithm is implemented using PowerPC processor which is available in Xilinx FPGAs of Virtex family.
A significant speedup of evolution is obtained in comparison with a highly optimized software implementation of CGP.

Keywords

hardware acceleration, regression problem, evolutionary design, image filter, fpga, powerpc

Published

2009

Pages

192–199

Proceedings

5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science

Conference

MEMICS'09 -- 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science

ISBN

978-80-87342-04-6

Publisher

Masaryk University

Place

Znojmo

BibTeX

@inproceedings{BUT34289,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="Efficient Hardware Accelerator for Symbolic Regression Problems",
  booktitle="5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2009",
  pages="192--199",
  publisher="Masaryk University",
  address="Znojmo",
  isbn="978-80-87342-04-6",
  url="https://www.fit.vut.cz/research/publication/9108/"
}

Files

pdf paper.pdf 546 kB

Projects

Design and hardware implementation of a patent-invention machine, GACR, Standardní projekty, GA102/07/0850, start: 2007-01-01, end: 2009-12-31, completed
Mathematical and Engineering Approaches to Developing Reliable and Secure Concurrent and Distributed Computer Systems, GACR, Doktorské granty, GD102/09/H042, start: 2009-01-30, end: 2012-12-31, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running

Research groups

Evolvable Hardware Research Group (RG EHW)

Departments

Department of Computer Systems (DCSY)