Result Details
Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time
Sekanina Lukáš, prof. Ing., Ph.D., DCSY (FIT)
Stareček Lukáš, Ing., Ph.D.
Recently, a method has been presented that allows a significant test application time reduction if some of gates of a digital circuit are reconfigured before test is applied. Selection of the gates for reconfiguration was performed using a very time consuming deterministic recursive search algorithm. In this paper, a new method is proposed for selection of the gates in order to reduce the test application time. The method utilizes an evolutionary algorithm which is able to discover very competitive reconfiguration strategies while the time of optimization is considerably reduced with respect to the original algorithm. Moreover, the user can easily balance the trade off between the number of test vectors and amount of logic that has to be reconfigured. Experimental results are reported for the ISCAS85 benchmark suite.
evolutionary algorithm, reconfiguration, testing, digital circuit
@inproceedings{BUT34847,
author="Jiří {Šimáček} and Lukáš {Sekanina} and Lukáš {Stareček}",
title="Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time",
booktitle="Evolvable Systems: From Biology to Hardware",
year="2010",
series="Lecture Notes in Computer Science",
volume="6274",
pages="214--225",
publisher="Springer Verlag",
address="Berlin",
isbn="978-3-642-15322-8",
url="https://www.fit.vut.cz/research/publication/9300/"
}Natural Computing on Unconventional Platforms, GACR, Standardní projekty, GAP103/10/1517, start: 2010-01-01, end: 2013-12-31, running
Secured, reliable and adaptive computer systems, BUT, Vnitřní projekty VUT, FIT-S-10-1, start: 2010-03-01, end: 2010-12-31, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running