Result Details

Recognizing Speed Limit Sign Numbers by Evolvable Hardware

TORRESEN, J.; BAKKE, J.; SEKANINA, L. Recognizing Speed Limit Sign Numbers by Evolvable Hardware. Lecture Notes in Computer Science, 2004, vol. 2004, no. 3242, p. 682-691. ISSN: 0302-9743.
Type
journal article
Language
English
Authors
Torresen Jim, prof. Dr. Ing.
Bakke Jorgen
Sekanina Lukáš, prof. Ing., Ph.D., DCSY (FIT)
Abstract

An automatic traffic sign detection system would be important in a driver assistance system. In this paper, an approach for detecting numbers on speed limit signs is proposed. Such a system would have to provide a high recognition performance in real-time. Thus, in this paper we propose to apply evolvable hardware for the classification of the numbers extracted from images. The system is based on incremental evolution of digital logic gates. Experiments show that this is a very efficient approach.

Keywords

evolvable hardware, incremental evolution, speed limit signs

URL
Published
2004
Pages
682–691
Journal
Lecture Notes in Computer Science, vol. 2004, no. 3242, ISSN 0302-9743
Book
Parallel Problem Solving from Nature
Publisher
Springer Verlag
Place
Berlin
BibTeX 
@article{BUT45728,
  author="Jim {Torresen} and Jorgen {Bakke} and Lukáš {Sekanina}",
  title="Recognizing Speed Limit Sign Numbers by Evolvable Hardware",
  journal="Lecture Notes in Computer Science",
  year="2004",
  volume="2004",
  number="3242",
  pages="682--691",
  issn="0302-9743",
  url="http://heim.ifi.uio.no/~jimtoer/PPSN04_Torresen.pdf"
}
Projects
Evolvable hardware based applications design methods, GACR, Postdoktorandské granty, GP102/03/P004, start: 2003-01-01, end: 2005-12-31, completed
Research groups
Evolvable Hardware Research Group (RG EHW)
Departments
Department of Computer Systems (DCSY)
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