Result Details

Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems

STRNADEL, J. Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems. In Proceedings of the 15th International IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Tallin: IEEE Computer Society, 2012. p. 121-126. ISBN: 978-1-4673-1188-5.
Type
conference paper
Language
English
Authors
Strnadel Josef, Ing., Ph.D., DCSY (FIT)
Abstract

In the paper, a concept and an early analysis of an embedded hardware/software architecture designed to prevent the software from both timing disturbances and interrupt overloads is outlined. The architecture is composed of an FPGA (MCU) used to run the hardware (software) part of an embedded application. Comparing to previous approaches, novelty of the architecture can be seen in the fact it is able to adapt interrupt service rates to the actual software load being monitored with no intrusion to the software. According to the actual software load it is able to buffer all interrupts and related data while the software is highly loaded and redirect the interrupts to the MCU as soon as the software becomes underloaded.

Keywords

embedded, limiter, interrupt, overload, monitoring, prevention, real-time

URL
Published
2012
Pages
121–126
Proceedings
Proceedings of the 15th International IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Conference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2012
ISBN
978-1-4673-1188-5
Publisher
IEEE Computer Society
Place
Tallin
DOI
10.1109/DDECS.2012.6219037
UT WoS
000312905700031
BibTeX 
@inproceedings{BUT91462,
  author="Josef {Strnadel}",
  title="Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems",
  booktitle="Proceedings of the 15th International IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)",
  year="2012",
  pages="121--126",
  publisher="IEEE Computer Society",
  address="Tallin",
  doi="10.1109/DDECS.2012.6219037",
  isbn="978-1-4673-1188-5",
  url="https://www.fit.vut.cz/research/publication/9868/"
}
Files
Projects
Advanced secured, reliable and adaptive IT, BUT, Vnitřní projekty VUT, FIT-S-11-1, start: 2011-01-01, end: 2013-12-31, completed
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, start: 2011-01-01, end: 2015-12-31, completed
National Support for Project Reduced Certification Costs Using Trusted Multi-core Platforms, MŠMT, Společné technologické iniciativy, 7H10013, start: 2010-04-01, end: 2013-03-31, running
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Computer Systems (DCSY)
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