Result Details
Test Platform for Fault Tolerant Systems Design Qualities Verification
Mičulka Lukáš, Ing., Ph.D., DCGM (FIT)
Kaštil Jan, Ing., Ph.D., DCSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
In this paper, a methodology for fault tolerant systems design qualities verification is presented together with recovery technique for fault tolerant system after soft errors occurrence in SRAM-based FPGA. First, the principles of test platform based on external SEU injector are presented, all components of test platform and their role during SEU simulation are described. Then, the recovery technique based on the generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The controller is used for the identification of faulty module in the fault tolerant system, reconfiguration of this module through ICAP interface and synchronization of the module after reconfiguration process with other modules in the system. The controller can be used for the identification of permanent faults in FPGA structure as well. The first experiments with test platform and reconfiguration controller are discussed in this paper.
controller, fault tolernat system, FPGA, SEU, injector, test platform
In this paper, a methodology for fault tolerant systems design qualities verification is presented together with recovery technique for fault tolerant system after soft errors occurrence in SRAM-based FPGA. First, the principles of test platform based on external SEU injector are presented, all components of test platform and their role during SEU simulation are described. Then, the recovery technique based on the generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The controller is used for the identification of faulty module in the fault tolerant system, reconfiguration of this module through ICAP interface and synchronization of the module after reconfiguration process with other modules in the system. The controller can be used for the identification of permanent faults in FPGA structure as well. The first experiments with test platform and reconfiguration controller are discussed in this paper.
@inproceedings{BUT91472,
author="Martin {Straka} and Lukáš {Mičulka} and Jan {Kaštil} and Zdeněk {Kotásek}",
title="Test Platform for Fault Tolerant Systems Design Qualities Verification",
booktitle="15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems",
year="2012",
pages="336--341",
publisher="IEEE Computer Society",
address="Tallin",
isbn="978-1-4673-1185-4"
}Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification, MŠMT, COST CZ (2011-2017), LD12036, start: 2012-03-01, end: 2015-11-30, completed
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