Course details

Advanced Digital Systems

PCS Acad. year 2023/2024 Winter semester 5 credits

This course is aimed at teaching advanced techniques of digital circuit design. Firstly, it presents a brief overview of basic approaches to modelling and simulation of digital circuits using the VHDL language and summarizes key properties of target technologies, such as ASIC and FPGA. Next, the course introduces advanced techniques of digital circuits minimization and synthesis (pipelining, retiming), which are supplemented by the application of constraints. The main part of the course is focused on modern approaches to the synthesis of digital circuits. This includes models and methods used for optimisation at logical level and with respect to target technology as well as approaches that build on synergy between synthesis and verification of digital circuits. Apart from these main topics, the course also touches some additional topics like low-power design and the verification of digital circuits based on the OVM methodology.


Course coordinator

Language of instruction



Examination (written)

Time span

  • 26 hrs lectures
  • 10 hrs pc labs
  • 16 hrs projects

Assessment points

  • 60 pts final exam (written part)
  • 18 pts mid-term test (written part)
  • 10 pts labs
  • 12 pts projects




Learning objectives

To give the students the knowledge of advanced digital systems design including hardware description languages, professional CAD tools, techniques for constrained design, and PLD technology.
The students are able to design complex constrained digital systems using contemporary design techniques and they know modern methods for synthesis and verification of these systems.

Why is the course taught

Design of real digital circuits often requires advanced knowledge, such as a deeper understanding of the synthesis process and its result, power-aware digital design, appropriate setting of constraints or functional verification. The goal of this course is to familiarize a student with these techniques and prepare him/her for a future profession in this area.

Prerequisite knowledge and skills

Digital system design, basic programming skills.

Study literature

  • Přednáškové materiály v elektronické podobě.
  • Khatri S. P., Gulati K. (eds.): Advanced Techniques in Logic Synthesis, Optimizations and Applications, ISBN 978-1-4419-7517-1, 2011
  • Rabaey J., Pedram M.: Low Power Design Methodologies, Kluwer, ISBN 0792396308, 1996

Fundamental literature

  • M. Morris Mano, Michael D. Ciletti: Digital Design, ISBN  978-9353062019, 2018
  • Micheli G., High-Level Synthesis from Algorithm to Digital Circuit, ISBN 978-1-4020-8587-1, 2008

Syllabus of lectures

  • Combinatorial and sequential logic design techniques, algorithms, and tools review.
  • Review of digital design target technologies (ASIC, FPGA).
  • Algorithms for minimization of digital circuits.
  • Advanced synthesis techniques (pipelining, retiming).
  • Constraint conditions.
  • Models and methods for modern synthesis of digital circuits (AIG, BDD, SAT solvers).
  • Modern synthesis of digital circuits (logic optimization).
  • Modern synthesis of digital circuits (optimization for target technology).
  • Synergy between synthesis and verification of digital circuits.
  • Low power design methodologies.
  • Development tools for FPGA and SoC.
  • Verification of digital circuits (OVM methodology).

Syllabus of computer exercises

  • Synthesis of the basic logic circuits, pipelining, retiming.
  • Constraint conditions.
  • Synthesis of basic digital circuits using ABC tool.
  • Synthesis of advanced digital circuits using ABC tool.
  • Verification of digital circuits.

Syllabus - others, projects and individual work of students

  • Individual project focused on synthesis of digital circuits.

Progress assessment

Written mid-term exam and project in due dates.

Presence in any form of instruction is not compulsory. An absence (and hence loss of points) can be compensated in the following ways: 

  1. presence in another laboratory group dealing with the same task. 
  2. showing a summary of results to the tutor at the next lab. 
  3. sending a short report (summarizing the results of the missed lab and answering the questions from the assignment) to the tutor, in 14 days after the missed lab.

Exam prerequisites

Requirements for class accreditation are not defined.


Mon comp.lab *) 1., 2. of lectures N103 N104 N105 14:0015:5020 1MIT 2MIT xx
Mon exam 2023-11-06 E105 18:0019:00 PCS - Půlsemestrální zkouška
Mon lecture 1., 2., 9., 12. of lectures E105 18:0019:5070 1MIT 2MIT NEMB NGRI xx Kořenek
Mon lecture 3., 4., 5., 6., 7., 13. of lectures E105 18:0019:5070 1MIT 2MIT NEMB NGRI xx Matoušek
Mon lecture 2023-11-20 E105 18:0019:5070 1MIT 2MIT NEMB NGRI xx Zachariášová
Mon lecture 2023-11-27 E105 18:0019:5070 1MIT 2MIT NEMB NGRI xx Kekely
Thu exam 2024-01-18 E104 08:0009:50 řádná
Thu comp.lab 3., 4. of lectures N103 10:0011:5020 1MIT 2MIT xx Kekely
Thu comp.lab 5., 6. of lectures N103 10:0011:5020 1MIT 2MIT xx Matoušek
Thu comp.lab 2023-09-21 N103 N104 N105 10:0011:5020 1MIT 2MIT xx
Thu comp.lab 2023-11-23 N103 10:0011:5020 1MIT 2MIT xx Zachariášová
It is not possible to register this class in Studis. (Some exercises may be opened later if needed, but this is not guaranteed.)

Course inclusion in study plans

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