Accelerated Network Technologies Research Group

Accelerated Network Technologies Research Group

The Accelerated Network Technologies (ANT) research group is focused on hardware acceleration of network devices and systems, which can be used for network monitoring and security. During more than fifteen years of existence, the ANT research team gained substantial expertise in the field of digital design and verification of hardware architectures, network performance monitoring and network security.

The primary research goal is to design new algorithms and architectures for cheaper and faster network devices and systems. The group deals with the design and optimization of architectures, primarily for FPGA technology. Network traffic analysis and detection of network threats use machine learning techniques and artificial intelligence.

Team members participated in the design and development of many unique devices and systems, which were successfully commercialized or used by security agencies to fight against cybercrime. For example, we contributed to the following research results:

Most of the research results were created in cooperation with the CESNET association within the Liberouter project. Two successful spin-off companies Flowmon Networks and Netcope Technologies were created based on the excellent research results and in cooperation with CESNET. Both companies are growing rapidly and have a global presence. The ANT research group has also research contracts with a number of companies, as well as with non-profit organizations.

Research interests

  • Hardware acceleration of time-critical operations in computer networks
  • Design and optimization of hardware architectures
  • Design of new devices and systems for network infrastructure
  • Network monitoring and security 
  • Utilization of machine learning techniques for network traffic analysis and network security

Selected Alumni

  • Jiří Tobola (CEO, Flowmon Networks) is a former PhD student and leader of the Liberouter project's firmware team focused on the development of hardware-accelerated IPv6 router. He received Thesis of the year award for his research in the field of hardware acceleration. As a co-founder and employee number one, Jiří accepted a challenge to develop a spin-off company back in 2007. His great leadership and technical background was an important contribution to make FlowMon Networks (former INVEA-TECH) a successful technology company with a worldwide presence. Currently, Jiří continues his mission in the company as its CEO.
  • Viktor Puš (Compiler Engineering Manager, Intel) participated on many research project within the ANT research group and Liberouter project. He started in the Liberouter project as a student and aimed his theses to the area of hardware-accelerated packet classification. He became our key person regarding the design of hardware systems. After leaving the research group and Liberouter project, he joined Netcope Technologies as CTO. Currently, he leads the team working on the P4 compiler in Intel.

Significant results

  • 2016: COMBO-CG card - was one of the first 100Gb FPGA acceleration cards, which was designed and produced with a great response in the research community and industry as well. The card was used in network monitoring and security products, for example, by one of the leading network test equipment manufacturers. It has been awarded by Czech Head price in the Industrie category for its unique features and successful application on the market.
  • 2018: Probe with L7 analysis - we designed and developed a unique probe for high-speed analysis of application protocols and lawful interception of network traffic. The probe has been designed based on the long-term cooperation with security agencies in the area of cybersecurity. Despite the probe being a small embedded device, it has unique features and high throughput. Therefore the authors have been awarded the Minister of the Interior Prize for outstanding results in the area of security research.
  • 2020: P4 compiler for FPGA technology - the application of hardware acceleration is usually limited by low flexibility and long development cycle. Network engineers are not able to program new hardware functions. New functions have to be implemented by experienced hardware designers, which takes time and money. To provide more flexibility for hardware acceleration, we participated in the research and development of a unique P4 language compiler, which was successfully commercialized by Netcope Technologies.


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