Result Details

Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability

ZACHARIÁŠOVÁ, M.; BOLCHINI, C.; KOTÁSEK, Z. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Karlovy Vary: IEEE Computer Society, 2013. p. 275-278. ISBN: 978-1-4673-6133-0.
Type
conference paper
Language
English
Authors
Zachariášová Marcela, Ing., Ph.D., DCSY (FIT)
Bolchini Cristiana
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
Abstract

As the complexity of current hardware systems rises rapidly, it is a challenging task to harden these systems against faults and to complete their verification and manufacturing test. Not only that verification and testing take a considerable amount of time but the number of design errors, faults, manufacturing defects and crosstalks increases with the rising complexity as well. Furthermore, when a system is designed to be reliable new issues come into play making the picture even more complex. In this paper we performed a detailed analysis of two approaches
devoted to verification of hardened systems, with respect to the
test set generation: the first one is based on classical Automatic
Test Pattern Generation, the second one on Constrained-random
Stimulus Generation. We evaluated their qualities as well as their
drawbacks and introduced few ideas about their combination
in order to create a new promising approach for verification of
reliable systems.

Keywords

ATPG, funkční verifikace.

Published
2013
Pages
275–278
Proceedings
IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
Conference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013
ISBN
978-1-4673-6133-0
Publisher
IEEE Computer Society
Place
Karlovy Vary
BibTeX 
@inproceedings{BUT103467,
  author="Marcela {Zachariášová} and Cristiana {Bolchini} and Zdeněk {Kotásek}",
  title="Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability",
  booktitle="IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems",
  year="2013",
  pages="275--278",
  publisher="IEEE Computer Society",
  address="Karlovy Vary",
  isbn="978-1-4673-6133-0"
}
Projects
Advanced secured, reliable and adaptive IT, BUT, Vnitřní projekty VUT, FIT-S-11-1, start: 2011-01-01, end: 2013-12-31, completed
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, start: 2011-01-01, end: 2015-12-31, completed
Manufacturable and Dependable Multicore Architectures at Nanoscale, MŠMT, COST, COST IC1103, start: 2011-06-15, end: 2015-12-31, completed
Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification, MŠMT, COST CZ (2011-2017), LD12036, start: 2012-03-01, end: 2015-11-30, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Information Systems (DIFS)
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