Result Details
NFA Reduction for Regular Expressions Matching Using FPGA
Žádník Martin, Ing., Ph.D., DCSY (FIT)
Kořenek Jan, doc. Ing., Ph.D., DCSY (FIT)
Many algorithms have been proposed to accelerate regular expression matching via mapping of a nondeterministic finite automaton into a circuit implemented in an FPGA. These algorithms exploit unique features of the FPGA to achieve high throughput. On the other hand the FPGA poses a limit on the number of regular expressions by its limited resources.
In this paper, we investigate applicability of NFA reduction techniques - a formal aparatus to reduce the number of states and transitions in NFA prior to its mapping into FPGA. The paper presents several NFA reduction techniques, each with a different reduction power and time complexity.
The evaluation utilizes regular expressions from Snort and L7 decoder. The best NFA reduction algorithms achieve more than 66% reduction in the number of states for a Snort ftp module. Such a reduction translates directly into 66% LUT and FF saving in the FPGA.
FPGA, NFA, Reduction, Regular expressions matching
@inproceedings{BUT104513,
author="Vlastimil {Košař} and Martin {Žádník} and Jan {Kořenek}",
title="NFA Reduction for Regular Expressions Matching Using FPGA",
booktitle="Proceedings of the 2013 International Conference on Field Programmable Technology",
year="2013",
pages="338--341",
publisher="IEEE Computer Society",
address="Kyoto",
isbn="978-1-4799-2199-7",
url="https://www.fit.vut.cz/research/publication/10306/"
}Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, start: 2011-01-01, end: 2015-12-31, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running