Result Details
Packet Processing on FPGA SoC with DPDK
Viktorin Jan, Ing., DCSY (FIT)
One of the most important topics of today is a packet processing in data centers with respect to the power consumption and efficient utilization of computational resources. The ARM architecture has proved to be an energy efficient computational system. Together with an integrated FPGA on a single die, it offers potentially a high performance with respect to the power consumption. DPDK - a set of libraries and drivers intended primarily for fast packet processing - is becoming to be a standard approach for packet processing, especially in data centers. In this paper, we exploit the potential of packet processing based on DPDK and FPGA SoC architectures. Especially, we aim at the potential of utilizing the ARM Cortex-A9 and Cortex-A53 CPUs.
DPDK, FPGA, SoC, ARM, packet processing
One of the most important topics of today is a data processing in data centers with respect to a low-power consumption and efficient utilization of computational resources. For such purposes, solutions with integrated FPGAs like the Xilinx Zynq and ZynqMP can be used. After few years of existance of such platforms, there is still no standard way of data processing on such platforms. The lack of a standard API for those purposes can be solved by utilizing the DPDK library intended for fast access to the hardware. This paper introduces a potential of utilizing the DPDK on Zynq and ZynqMP-bases systems.
@inproceedings{BUT130979,
author="Jan {Kořenek} and Jan {Viktorin}",
title="Packet Processing on FPGA SoC with DPDK",
booktitle="26th International Conference on Field-Programmable Logic and Applications",
year="2016",
pages="578--579",
publisher="École Polytechnique Fédérale de Lausanne",
address="Lausanne",
doi="10.1109/FPL.2016.7577395",
isbn="978-2-8399-1844-2",
url="http://ieeexplore.ieee.org/document/7577395/"
}IT4Innovations excellence in science, MŠMT, Národní program udržitelnosti II, LQ1602, start: 2016-01-01, end: 2020-12-31, completed
Smart Application Aware Embedded Probes, MV, Bezpečnostní výzkum České republiky 2015-2020, VI20152019001, start: 2015-09-01, end: 2019-05-31, completed