Result Details
A Tool for VLIW Processors Code Optimizing
MEGO, R.; FRÝZA, T. A Tool for VLIW Processors Code Optimizing. In Proceedings of the 13th International Conference on Computer Engineering and Systems (ICCES 2018). Cairo, Egypt: Ain Shams University, 2019. p. 601-604. ISBN: 978-1-5386-5111-7.
Type
conference paper
Language
English
Authors
Mego Roman, Ing., Ph.D.
Frýza Tomáš, doc. Ing., Ph.D., UREL (FEEC)
Frýza Tomáš, doc. Ing., Ph.D., UREL (FEEC)
Abstract
The paper demonstrates the behavior of low- and high-level programming languages on the multicore digital signal processors based on Very Long Instruction Word architecture. The aim of the paper is to present a tool that can be used to implement any digital signal processing algorithm on such processors with efficiency of the low-level languages, but with the advantages of the high-level programming languages. Preliminary result is the software that uses a signal-flow graph approach to describe an algorithm, generates low-level assembly code and provides (graphical) information about the algorithm.
Keywords
VLIW, low-level, assembly, C6678, FFT, DCT
URL
Published
2019
Pages
601–604
Proceedings
Proceedings of the 13th International Conference on Computer Engineering and Systems (ICCES 2018)
Conference
13th International Conference on Computer Engineering and Systems (ICCES)
ISBN
978-1-5386-5111-7
Publisher
Ain Shams University
Place
Cairo, Egypt
DOI
UT WoS
000465792300097
EID Scopus
BibTeX
@inproceedings{BUT155771,
author="Roman {Mego} and Tomáš {Frýza}",
title="A Tool for VLIW Processors Code Optimizing",
booktitle="Proceedings of the 13th International Conference on Computer Engineering and Systems (ICCES 2018)",
year="2019",
pages="601--604",
publisher="Ain Shams University",
address="Cairo, Egypt",
doi="10.1109/ICCES.2018.8639186",
isbn="978-1-5386-5111-7",
url="https://ieeexplore.ieee.org/document/8639186"
}
Departments