Detail výsledku

A Tool for VLIW Processors Code Optimizing

MEGO, R.; FRÝZA, T. A Tool for VLIW Processors Code Optimizing. In Proceedings of the 13th International Conference on Computer Engineering and Systems (ICCES 2018). Cairo, Egypt: Ain Shams University, 2019. p. 601-604. ISBN: 978-1-5386-5111-7.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Mego Roman, Ing., Ph.D., UREL (FEKT)
Frýza Tomáš, doc. Ing., Ph.D., UREL (FEKT)
Abstrakt

The paper demonstrates the behavior of low- and high-level programming languages on the multicore digital signal processors based on Very Long Instruction Word architecture. The aim of the paper is to present a tool that can be used to implement any digital signal processing algorithm on such processors with efficiency of the low-level languages, but with the advantages of the high-level programming languages. Preliminary result is the software that uses a signal-flow graph approach to describe an algorithm, generates low-level assembly code and provides (graphical) information about the algorithm.

Klíčová slova

VLIW, low-level, assembly, C6678, FFT, DCT

URL
Rok
2019
Strany
601–604
Sborník
Proceedings of the 13th International Conference on Computer Engineering and Systems (ICCES 2018)
Konference
13th International Conference on Computer Engineering and Systems (ICCES)
ISBN
978-1-5386-5111-7
Vydavatel
Ain Shams University
Místo
Cairo, Egypt
DOI
10.1109/ICCES.2018.8639186
UT WoS
000465792300097
EID Scopus
2-s2.0-85063155102
BibTeX 
@inproceedings{BUT155771,
  author="Roman {Mego} and Tomáš {Frýza}",
  title="A Tool for VLIW Processors Code Optimizing",
  booktitle="Proceedings of the 13th International Conference on Computer Engineering and Systems (ICCES 2018)",
  year="2019",
  pages="601--604",
  publisher="Ain Shams University",
  address="Cairo, Egypt",
  doi="10.1109/ICCES.2018.8639186",
  isbn="978-1-5386-5111-7",
  url="https://ieeexplore.ieee.org/document/8639186"
}
Pracoviště
Ústav radioelektroniky (UREL)
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