Result Details

New approach to the FPGA testing based on the Boundary Scan

KOTÁSEK, Z.; TUPEC, P. New approach to the FPGA testing based on the Boundary Scan. Proceedings of 38th International Conference MOSIS'04. Ostrava: Marq software s.r.o., 2004. p. 120-123. ISBN: 80-85988-98-4.
Type
conference paper
Language
English
Authors
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT)
Tupec Pavel, Ing., CVP - Univerzita tř.vě (CECC), DCSY (FIT)
Abstract

In the paper, a method enabling to verify the functionality of an FPGAdesign is presented. This method is based on the formal modelconstruction of the register transfer (RT) level digital circuit. Thisnew approach allows FPGA designers to debug and verify their hardwarebeing developed. A Boundary scan is used as a communication interface.As an input, a digital circuit structure at RT level designed using anyDfT technique is assumed.

Keywords

JTAG, debugger, RT level, boundary scan

Annotation

FPGA testing

Published
2004
Pages
120–123
Proceedings
Proceedings of 38th International Conference MOSIS'04
Conference
MOSIS 2004 - Modelling and Simulation of Systems
ISBN
80-85988-98-4
Publisher
Marq software s.r.o.
Place
Ostrava
BibTeX 
@inproceedings{BUT16896,
  author="Zdeněk {Kotásek} and Pavel {Tupec}",
  title="New approach to the FPGA testing based on the Boundary Scan",
  booktitle="Proceedings of 38th International Conference MOSIS'04",
  year="2004",
  pages="120--123",
  publisher="Marq software s.r.o.",
  address="Ostrava",
  isbn="80-85988-98-4"
}
Departments
Department of Computer Systems (DCSY)
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