Detail výsledku

New approach to the FPGA testing based on the Boundary Scan

KOTÁSEK, Z.; TUPEC, P. New approach to the FPGA testing based on the Boundary Scan. Proceedings of 38th International Conference MOSIS'04. Ostrava: Marq software s.r.o., 2004. p. 120-123. ISBN: 80-85988-98-4.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Kotásek Zdeněk, doc. Ing., CSc., UPSY (FIT)
Tupec Pavel, Ing., CVP - Univerzita tř.vě (CVP), UPSY (FIT)
Abstrakt

In the paper, a method enabling to verify the functionality of an FPGAdesign is presented. This method is based on the formal modelconstruction of the register transfer (RT) level digital circuit. Thisnew approach allows FPGA designers to debug and verify their hardwarebeing developed. A Boundary scan is used as a communication interface.As an input, a digital circuit structure at RT level designed using anyDfT technique is assumed.

Klíčová slova

JTAG, debugger, RT level, boundary scan

Rok
2004
Strany
120–123
Sborník
Proceedings of 38th International Conference MOSIS'04
Konference
MOSIS 2004 - Modelling and Simulation of Systems
ISBN
80-85988-98-4
Vydavatel
Marq software s.r.o.
Místo
Ostrava
BibTeX 
@inproceedings{BUT16896,
  author="Zdeněk {Kotásek} and Pavel {Tupec}",
  title="New approach to the FPGA testing based on the Boundary Scan",
  booktitle="Proceedings of 38th International Conference MOSIS'04",
  year="2004",
  pages="120--123",
  publisher="Marq software s.r.o.",
  address="Ostrava",
  isbn="80-85988-98-4"
}
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru