Result Details

Testing PCBs Based on Boundary Scan and EDIF Data Analysis

KOTÁSEK, Z.; TOMÍŠEK, P.; ZBOŘIL, F. Testing PCBs Based on Boundary Scan and EDIF Data Analysis. Proceedings of the DDECS'98. Szczyrk: unknown, 1998. p. 95-101. ISBN: 83-908409-6-0.
Type
conference paper
Language
English
Authors
Kotásek Zdeněk, doc. Ing., CSc.
Tomíšek Petr
Zbořil František, doc. Ing., CSc.
Abstract

The paper describes a practical approach to testing PCBs with Xilinx FPGAs. The approach is based on a PCB netlist analysis which is an integral part of EDIF data (Electronic Design Interchange Format), revealing the existing connections on the PCB through the Boundary Scan chain and comparing the two results. It is also supposed that the developed software tools will be used for debugging PCBs with Xilinx FPGAs. The goal of the research activities is to develop an easy to use, efficient and user friendly software tools.

Keywords

Boundary Scan, PCBs Testing, Xilinx FPGAs, EDIF Data Analysis

Published
1998
Pages
95–101
Proceedings
Proceedings of the DDECS'98
Conference
DDECS 1998
ISBN
83-908409-6-0
Publisher
unknown
Place
Szczyrk
BibTeX 
@inproceedings{BUT191444,
  author="Zdeněk {Kotásek} and Petr {Tomíšek} and František {Zbořil}",
  title="Testing PCBs Based on Boundary Scan and EDIF Data Analysis",
  booktitle="Proceedings of the DDECS'98",
  year="1998",
  pages="95--101",
  publisher="unknown",
  address="Szczyrk",
  isbn="83-908409-6-0"
}
Projects
Methodology and tools for digital circuits testability analysis, GACR, Standardní projekty, GA102/98/1463, start: 1998-01-01, end: 2006-03-31, completed
Research groups
Intelligent Systems Research Group (RG INTSYS)
Departments
Faculty of Information Technology (FIT)
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