Result Details

Web-Based Simulator of Superscalar RISC-V Processors

JAROŠ, J.; MAJER, M.; HORKÝ, J.; VÁVRA, J. Web-Based Simulator of Superscalar RISC-V Processors. Atlanta, GA: 2024. p. 1-2.
Type
presentation, poster
Language
English
Authors
Jaroš Jiří, prof. Ing., Ph.D., DCSY (FIT)
Majer Michal, Ing.
Horký Jakub, Ing.
Vávra Jan, Ing.
Abstract

Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar processors and HW-SW co-design. With customizable processor architecture, full C compiler support, and detailed performance statistics, this tool offers a comprehensive learning experience. Enjoy the convenience of a modern, web-based GUI to enhance your understanding and skills.

Keywords

Web-based simulator, RISC-V processor, superscalar processor 

URL
Published
2024
Pages
1–2
Conference
The International Conference for High Performance Computing, Networking, Storage, and Analysis
Place
Atlanta, GA
BibTeX 
@misc{BUT196523,
  author="Jiří {Jaroš} and Michal {Majer} and Jakub {Horký} and Jan {Vávra}",
  title="Web-Based Simulator of Superscalar RISC-V Processors",
  year="2024",
  pages="1--2",
  address="Atlanta, GA",
  url="https://sc24.supercomputing.org/proceedings/poster/poster_files/post150s2-file3.pdf"
}
Files
Projects
Application-specific HW/SW architectures and their applications, BUT, Vnitřní projekty VUT, FIT-S-23-8141, start: 2023-03-01, end: 2026-02-28, running
Departments
Department of Computer Systems (DCSY)
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