Detail výsledku

Web-Based Simulator of Superscalar RISC-V Processors

JAROŠ, J.; MAJER, M.; HORKÝ, J.; VÁVRA, J. Web-Based Simulator of Superscalar RISC-V Processors. Atlanta, GA: 2024. p. 1-2.
Typ
prezentace, poster
Jazyk
anglicky
Autoři
Jaroš Jiří, prof. Ing., Ph.D., UPSY (FIT)
Majer Michal, Ing.
Horký Jakub, Ing.
Vávra Jan, Ing.
Abstrakt

Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar processors and HW-SW co-design. With customizable processor architecture, full C compiler support, and detailed performance statistics, this tool offers a comprehensive learning experience. Enjoy the convenience of a modern, web-based GUI to enhance your understanding and skills.

Klíčová slova

Web-based simulator, RISC-V processor, superscalar processor 

URL
Rok
2024
Strany
1–2
Konference
The International Conference for High Performance Computing, Networking, Storage, and Analysis
Místo
Atlanta, GA
BibTeX 
@misc{BUT196523,
  author="Jiří {Jaroš} and Michal {Majer} and Jakub {Horký} and Jan {Vávra}",
  title="Web-Based Simulator of Superscalar RISC-V Processors",
  year="2024",
  pages="1--2",
  address="Atlanta, GA",
  url="https://sc24.supercomputing.org/proceedings/poster/poster_files/post150s2-file3.pdf"
}
Soubory
Projekty
Application-specific HW/SW architectures and their applications, VUT, Vnitřní projekty VUT, FIT-S-23-8141, zahájení: 2023-03-01, ukončení: 2026-02-28, řešení
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru