Result Details

Design of Phase Locked-Loop for Very Slow Sine-Wave Signals

HÁZE, J.; VRBA, R.; PROKOP, R. Design of Phase Locked-Loop for Very Slow Sine-Wave Signals. In Proceedings of IEEE International Conference on Systems ICONS 2008. Cancun: IEEE, 2008. p. 67-71. ISBN: 978-0-7695-3105-2.
Type
conference paper
Language
English
Authors
Háze Jiří, doc. Ing., Ph.D., UMEL (FEEC)
Vrba Radimír, prof. Ing., CSc., UMEL (FEEC)
Prokop Roman, Ing., Ph.D., UMEL (FEEC)
Abstract

The paper describes the design procedure of phase locked loop (PLL). This PLL is used in band-pass sigma-delta modulator to synchronise the input slow sine-wave signal with driving clock of modulator. It generates 62,5 kHz rectangle driving signal. The paper also shows simulation results, which confirm the design process .

Keywords

phase locked-loop

Published
2008
Pages
67–71
Proceedings
Proceedings of IEEE International Conference on Systems ICONS 2008
Conference
Third International Conference on Systems
ISBN
978-0-7695-3105-2
Publisher
IEEE
Place
Cancun
BibTeX 
@inproceedings{BUT28637,
  author="Jiří {Háze} and Radimír {Vrba} and Roman {Prokop}",
  title="Design of Phase Locked-Loop for Very Slow Sine-Wave Signals",
  booktitle="Proceedings of IEEE International Conference on Systems ICONS 2008",
  year="2008",
  pages="67--71",
  publisher="IEEE",
  address="Cancun",
  isbn="978-0-7695-3105-2"
}
Departments
Department of Microelectronics (UMEL)
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