Detail výsledku

Design of Phase Locked-Loop for Very Slow Sine-Wave Signals

HÁZE, J.; VRBA, R.; PROKOP, R. Design of Phase Locked-Loop for Very Slow Sine-Wave Signals. In Proceedings of IEEE International Conference on Systems ICONS 2008. Cancun: IEEE, 2008. p. 67-71. ISBN: 978-0-7695-3105-2.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Háze Jiří, doc. Ing., Ph.D., UMEL (FEKT)
Vrba Radimír, prof. Ing., CSc., UMEL (FEKT)
Prokop Roman, Ing., Ph.D., UMEL (FEKT)
Abstrakt

The paper describes the design procedure of phase locked loop (PLL). This PLL is used in band-pass sigma-delta modulator to synchronise the input slow sine-wave signal with driving clock of modulator. It generates 62,5 kHz rectangle driving signal. The paper also shows simulation results, which confirm the design process .

Klíčová slova

phase locked-loop

Rok
2008
Strany
67–71
Sborník
Proceedings of IEEE International Conference on Systems ICONS 2008
Konference
Third International Conference on Systems
ISBN
978-0-7695-3105-2
Vydavatel
IEEE
Místo
Cancun
BibTeX 
@inproceedings{BUT28637,
  author="Jiří {Háze} and Radimír {Vrba} and Roman {Prokop}",
  title="Design of Phase Locked-Loop for Very Slow Sine-Wave Signals",
  booktitle="Proceedings of IEEE International Conference on Systems ICONS 2008",
  year="2008",
  pages="67--71",
  publisher="IEEE",
  address="Cancun",
  isbn="978-0-7695-3105-2"
}
Pracoviště
Ústav mikroelektroniky (UMEL)
Nahoru