Result Details

Design and Optimization of ColdFire CPU Arithmetic Logical Unit

ADAMEC, F.; FRÝZA, T. Design and Optimization of ColdFire CPU Arithmetic Logical Unit. In Proceedings of 16th International Conference Mixed Design of Integrated Circuits and Systems. Lodz (Poland): 2009. p. 699-702. ISBN: 978-83-928756-0-4.
Type
conference paper
Language
English
Authors
Adamec Filip, Ing., UREL (FEEC)
Frýza Tomáš, doc. Ing., Ph.D., UREL (FEEC)
Abstract

This article describes design of ColdFire microprocessor ALU (Arithmetic Logical Unit) in VHDL language and presents an optimization to obtain maximum performance in Xilinx Virtex IV FPGA. The basic function of ALU is explained. There are described the instructions which any ALU must handle and some possibility how to design it. The advantages and disadvantages of performance are obtained as well.

Keywords

Arithmetic Logical Unit; VHDL; FPGA; instructions

Published
2009
Pages
699–702
Proceedings
Proceedings of 16th International Conference Mixed Design of Integrated Circuits and Systems
Conference
16th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 2009)
ISBN
978-83-928756-0-4
Place
Lodz (Poland)
UT WoS
000275900300137
BibTeX 
@inproceedings{BUT32734,
  author="Filip {Adamec} and Tomáš {Frýza}",
  title="Design and Optimization of ColdFire CPU Arithmetic Logical Unit",
  booktitle="Proceedings of 16th International Conference Mixed Design of Integrated Circuits and Systems",
  year="2009",
  pages="699--702",
  address="Lodz (Poland)",
  isbn="978-83-928756-0-4"
}
Departments
Department of Radio Electronics (UREL)
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